The present invention relates to semiconductor devices and can be utilized preferably for a semiconductor device including, for example, a nonvolatile memory cell.
There exists an element that stores data (also called information) as a nonvolatile memory cell by accumulating charges such as electrons in a conductor film having a floating state.
For example, Japanese Patent Laid-Open No. 2011-9454 (Patent Document 1) discloses a technique in which a floating gate electrode is disposed so as to overlap with a part of a first n-well and a second n-well and stored data is erased by means of applying a positive voltage to the second n-well and emitting electrons of the floating gate electrode to the second n-well.
In addition, U.S. Pat. No. 6,711,064 (Patent Document 2) discloses an EEPROM (Electrically Erasable Programmable Read-Only Memory) provided with an erase gate.
Furthermore, US Patent Application Publication 2008/0017917 (Patent Document 3) discloses a nonvolatile memory provided with a floating gate transistor, a dielectric layer, and a conductive plug formed over a floating gate as an erase gate.